

module Divider
    #(
        parameter IWID=12,
        parameter OWID=32
    )
    (
        input wire signed [IWID-1:0] i_div1,
        input wire signed [IWID-1:0] i_div2,
        input wire i_clk,
        input wire i_rst,
        output reg signed [OWID-1:0] o_result
    );
    wire signed [OWID-1:0] div_result;

    assign div_result=i_div1/i_div2;

    always@(posedge i_clk or posedge i_rst) begin
        if(i_rst) begin
            o_result<='b0;
        end
        else begin
            o_result<=div_result;
        end
    end

endmodule
